Design of A Digital PLL with Divide by 4/5 Prescaler

Phase Locked Loops (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal.A phase locked loop can track input frequency or it can generate a frequency that is the multiple of input frequency .PLLs are widely employed in radio,tele communications,computers etc.In order to overcome the disadvantage of analog PLLs such as the effect of leakage current and temperature, an all digital PLL is preferred here.It eliminates the problems in clocking like clock skew and jitter.The PLL is designed digitally with a divide by 4/5 prescaler in the frequency divider section.It divides the DCO frequency with two consecutive integers.The proposed method is designed in verilog and is implemented in xilinix. The major factor to be considered here is lock time.The lock time achieved here is 19.05μs